Regression testing is part of all standard design and verification flows, and usually involves a large portion of computer resources allocated to verification.
These regression test suites are often made of concatenation of tests used to individually validate RTL pieces of a design, rather than being developed with consideration of global system functionality. As a result, a lot of redundancy and overlapping tests waste precious simulation time.

VN-Optimize uses coverage information to analyze the test benches and to identify a sorted set of tests that meet predefined regression goals. VN-Optimize combines high performance storage techniques with advanced set theory algorithms to provide the highest capacity and performance.

By using various coverage metrics to find the optimal set of tests, VN-Optimize allows bug tracking in less time, with fewer simulation resources. In addition, cross-referencing lines of RTL code to the test benches covering them achieves faster convergence of ECO iterations.

• Dramatically cuts regression testing time by finding the optimal set of tests for the entire design, or selected instances or modules
• Increases ECO productivity by pin-pointing the set of tests which best covers specific parts of the design code
• Enables incremental and distributed work with capabilities to merge and combine results for total coverage information
• Fully integrated with VN-Cover: seamlessly uses coverage analysis results from Verilog, VHDL and mixed-language simulation

Sereda Technologies Ltd

PO Box 444
Wokingham Berks UK
RG40 1ZR
Tel: +44 118 9782016
Fax: +44 118 9890424
Email:contact@ sereda-tech.co.uk