Logic simulation remains the dominant method to verify the functionality of a design and to perform regression testing when the RTL code changes. To achieve high quality and completeness of this process, it is critical to use the highest quality metrics available from an efficient tool and to accurately measure coverage with minimal impact to simulation performance.
VN-Cover is a code and FSM coverage tool that identifies any unverified parts of a simulated HDL design. VN-Cover includes the most comprehensive set of metrics in the industry, which include line, statement, branch, condition, path, toggle, triggering, signal trace and FSM state, arc and path.

In addition, the tool offers advanced features such as Deglitch and Coverability Analysis option, aimed at increasing measured coverage accuracy.

VN-Cover seamlessly works with all leading simulators to measure coverage on VHDL, Verilog, SystemVerilog and mixedlanguage designs. It is the only vendor-neutral coverage tool that works across simulators, languages and platforms, and can be also utilized with hardware-accelerated verification environments.

• Quantifies verification completeness by using the industry’s most comprehensive and accurate set of metrics
• Performs extensive analysis on automatically extracted finite state machines (FSMs)
• Filters out false-positive coverage information due to zero-delay glitches
• Determines uncoverable areas and updates the final coverage ratio
• Helps decrease regression time using effective test-optimization capability
• Works across design languages and simulation platforms

Sereda Technologies Ltd

PO Box 444
Wokingham Berks UK
RG40 1ZR
Tel: +44 118 9782016
Fax: +44 118 9890424
Email:contact@ sereda-tech.co.uk