The time to develop a high-end FPGA, ASIC, or SoC device is becoming longer than the life cycle of the device primarily due to the amount of time it takes to verify the functionality of the device.
Today, verifying high-end designs typically consumes 70% or more of the total development time and resources. Using VN-Control on designs interfacing with buses in conjunction with bus functional models and monitors can minimize the time required to generate high quality tests.

• Quickly verifies interfaces and module interaction of bus-based designs
• Automatically generates real-world system-level tests to detect corner case bugs
• Integrates easily into existing verification environment
• Ready-to-use without the need to learn new languages
• Leverages models and monitors from TransEDA, third-party, or user created
• Works with all leading simulators

Sereda Technologies Ltd

PO Box 444
Wokingham Berks UK
RG40 1ZR
Tel: +44 118 9782016
Fax: +44 118 9890424
Email:contact@ sereda-tech.co.uk