Deploying a robust HDL checking methodology for a SOC design flow is generally accepted to be the quickest and most cost-effective method of finding design errors. When simple design errors are discovered early in the design process, the turnaround time for bug fixing is reduced and downstream verification productivity increased.

VN-Check is a configurable HDL rule checker that analyzes VHDL, Verilog and SystemVerilog designs to provide concise reports on problematic areas. VN-Check's rules can be configured at a very detailed level to match the design flow requirements.
Engineers can organize rules into rule-sets and share them among design groups to enforce consistent HDL coding style. This practice speeds verification, helps design-for-reuse and provides valuable feedback to HDL designers.

• Finds register-transfer level (RTL) design errors quickly and effectively
• Improves overall functional verification by increasing RTL code quality
• Raises confidence in internally developed blocks as well as third-party IP
• Promotes best-practice coding style sharing across design teams
• Fits in all verification flows with numerous, configurable checks and rule-sets

Sereda Technologies Ltd

PO Box 444
Wokingham Berks UK
RG40 1ZR
Tel: +44 118 9782016
Fax: +44 118 9890424
Email:contact@ sereda-tech.co.uk