TransEDA

Coverability Analysis

Code coverage, associated with simulation, is the most popular way for engineers to measure how well a test suite exercises the RTL code of a design.

Measuring coverage is more than simply counting lines of code that the simulator has hit. Many metrics are involved (statement, branch, toggle, FSM, condition, etc...) and the finer grain one, expression coverage, must be used to ensure the most accurate measurement of design activity.

The difficulties usually arise when getting close to the coverage sign-off point. It takes a lot of time and tremendous efforts to find the right test sequence that can trigger the last few uncovered items. Even more time is wasted trying to cover branches or expression terms that are not attainable.
Coverability analysis saves weeks of debug and test bench tuning, by providing a formal proof of whether an uncovered item is reachable or not.

Formally determines uncoverable branches and expression terms in RTL designs
Ensures faster convergence to meet sign-off coverage targets based on the industry’s most comprehensive set of coverage metrics
Helps to improve the test suite by providing VCD and testbench files that illustrate how to exercise coverable items
Easily deployable: no new languages or new technologies to master
Automatic reporting and filtering of uncoverable code constructs

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