Assertain is an innovative environment dedicated to measuring the completeness of the verification of digital SoC designs, in order to secure a faster and safer path to verification closure.
Covering all front-end design stages from original text specification through to validated RTL, Assertain monitors, measures and helps manage the verification process in one integrated environment.

The tool seamlessly brings together rule, protocol and assertion checking; code and assertion coverage; design and assertion coverability analysis; test suite optimization; and specification coverage using proven requirements traceability techniques.

Assertain exists in three versions, each of them corresponding to a well defined type of application. Assertain HDL, the entry level of the Assertain product line, has been specially developed for design and verification engineers who need the best-in-class code coverage solution combined with test suite optimization capabilities and an extensive RTL analyzer.

• Quantifies simulation completeness using the most comprehensive and accurate set of code coverage metrics
• Screens RTL code using extensive rule checking capabilities completed by automatic formal analysis
• Cuts weeks off the verification schedule by deploying an embedded formal engine to perform coverability analysis
• Enables independent coverage measurement and results merging from heterogeneous simulation environments
• Straightforward to integrate into existing verification flows as the tool works with all leading simulators
• Allows easy management and visualization of verification closure criteria in a single, coherent environment

Sereda Technologies Ltd

PO Box 444
Wokingham Berks UK
RG40 1ZR
Tel: +44 118 9782016
Fax: +44 118 9890424
Email:contact@ sereda-tech.co.uk