TransEDA

Assertain-ABV

Assertain is an innovative environment dedicated to measuring the completeness of the verification of digital SoC designs, in order to secure a faster and safer path to verification closure.
Covering all front-end design stages from original text specification through to validated RTL, Assertain monitors, measures and helps manage the verification process in one integrated environment.

The tool seamlessly brings together rule, protocol and assertion checking; code and assertion coverage; design and assertion coverability analysis; test suite optimization; and specification coverage using proven requirements traceability techniques.

Quantifies verification completeness using the most comprehensive and accurate set of code FSM, assertion and functional coverage metrics
Screens RTL code using extensive rule checking capabilities completed by automatic formal analysis
Cuts weeks off the verification schedule by deploying an embedded formal engine to performcoverability analysis
Straightforward to integrate into existing verification flows as the tool works with all leading simulators
Allows easy management and visualization of verification closure criteria in a single, coherent environment
Links specifications, assertions, RTL code and test benches using unique requirements traceability technology

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