VirtualScan (TM) is SynTest’s solution to combat the increase in test data volume and test cycle volume.
With VirtualScan (TM) an extremely large number of short scan chains within the SOC can be virtually accessed from outside the chip with a limited number of pins assigned as scan pins.
Inside the chip, SynTest’s new patent-pending circuitry is used to broadcast each external scan-input chain to a user-selectable number of internal scan chains and at the other end, compact them into the original number of external scan chains.

An evaluation on a 2-million gate design using VirtualScan (TM) showed a 22x reduction in test time. Further, the static and dynamic compaction capabilities of SynTest’s powerful ATPG tool help reduce pattern sizes, leading to overall reduction in test costs.

BENEFITS OF VIRTUALSCAN (TM)

• * Reduces cost of semiconductor testing - 5x to 50x
• Extends life of existing ATE for large SOC designs
• Smaller test data volume and shorter test time
• Short test development time with no iterations
• High fault coverage
• Predictable and very low hardware overhead
• Smooth migration into existing scan ATPG flow
• Diagnosis support

Sereda Technologies Ltd

PO Box 444
Wokingham Berks UK
RG40 1ZR
Tel: +44 118 9782016
Fax: +44 118 9890424
Email:contact@ sereda-tech.co.uk