Today, integrated chips with multi-million gates, containing logic, memory and analog functions are becoming commonplace.
At the same time, meeting tight time-to-market schedules, controlling costs and maintaining high quality standards are critical to the success of any such new development. Further, nanometer technology has become a reality.

However, cost of semiconductor testing has been increasing steadily over the past few years making it a major part of the overall manufacturing cost of chips.
The increase in size and complexity of new chips calls for a radical approach to enable companies developing million-gate ASICs to speed their products through the test process more rapidly without having to upgrade to more expensive, latest generation Automatic Test Equipment (ATE) or to expand pin-electronics on existing ATE.

For ASICs designed with feature size greater than 130 nm, testing for stuck-at faults and IDDQ is adequate to ensure acceptable quality levels.
However, in ASIC’s designed for 130 nm or below, many manufacturing defects are no longer static. They become delay defects and it becomes necessary to use delay tests to detect the transition faults and path delay faults. Often bridging tests are also required.
Since these delay tests are more complicated than tests for stuck-at faults, many more test patterns are required resulting in more time on ATE and more memory to store patterns. The end result being increased test cost.

It is in this environment that UltraScan together with VirtualScan help in reducing the cost of ASIC testing. UltraScan with its Time-Division De-Multiplexing (TDDM) and Multiplexing (TDM) circuits is able to take advantage of the unutilized bandwidth available on high-speed channels on the ATE during low speed scan-shift operation, and thereby offer overall shorter load times of scan chains.

Benefits of UltraScan (TM) with VirtualScan (TM)

• Reduces test data volume of semiconductor testing - 5x to 50x
• Reduces test time - 50x to 500x
• Extends life of existing ATE for large SOC designs
• Reduces test time for all scan designs with ATPG compression structures
• A small number of high-speed I/O pads are adequate to run a scan ATPG test for a design with a large number of internal scan chains of shorter length
• Pin reduction realized through TDDM/TDM circuitry
• Overall shorter test load times by taking advantage of the unutilized bandwidth available on high-speed channels on the ATE during low-speed scan-shift operation
• High fault coverage
• Better delay fault coverage for highspeed I/O pads on the device
• Short test development time with no iterations
• Predictable & low hardware overhead
• Smooth migration into existing scan ATPG flow
• Diagnosis support

Sereda Technologies Ltd

PO Box 444
Wokingham Berks UK
RG40 1ZR
Tel: +44 118 9782016
Fax: +44 118 9890424
Email:contact@ sereda-tech.co.uk