Today, integrated chips with multi-million gates, containing logic, memory and analog functions are becoming commonplace.
At the same time, meeting tight time-to-market schedules, controlling costs and maintaining high quality standards are critical to the success of any such new development.

Design-for-Test (DFT) tools and methodologies enable automation of many aspects of the structural testing process, ensuring that the chip comes through tape-out and manufacturing on time, and of proper quality.
DFT tools enable creation of efficient test patterns that detect most major manufacturing defects.
Effective DFT methodologies available today for structural testing include scan synthesis and ATPG (Automatic Test Pattern Generation), logic BIST (Built-in Self- Test) and fault simulation.

TurboScan is an advanced full-scan test suite. It includes a scan synthesizer and an Automatic Test Pattern Generator.
The scan synthesizer supports full scan methodologies. The ATPG engine uses advanced search and compaction algorithms to produce very high fault coverage test patterns with very concise pattern sizes.

BENEFITS OF TURBOSCAN

• Improved design quality through very high fault coverage test patterns
• Generates Stuck-at, transition, bridging fault, Iddq, path-delay patterns
• Reduced test costs - shorter test times and reduced test data volumes
• Easy to integrate into existing design flow
• ATPG patterns can also be generated for designs that have scan chains inserted using other vendor’s scan synthesis tools.
• Minimum Silicon Usage/Overhead
• Short CPU Times

Sereda Technologies Ltd

PO Box 444
Wokingham Berks UK
RG40 1ZR
Tel: +44 118 9782016
Fax: +44 118 9890424
Email:contact@ sereda-tech.co.uk