Today, integrated chips with multi-million gates, containing logic, memory and analog functions are becoming common place. At the same time, controlling costs and maintaining high quality standards are critical to the success of any such new development.
In such situations, fault simulation plays an important role in providing accurate fault coverage for areas not covered by scan or BIST.

High Performance Fault Simulation
TurboFault(TM) combines high performance, versatility and accuracy for classical test fault grading.

TurboFault(TM) is the fastest concurrent fault simulator based on the latest advances in cycle-based simulation technology. It simulates even faster than existing expensive hardware-accelerated fault simulators.

TurboFault(TM) supports synchronous and asynchronous designs at the gate level, including tri-state gates, latches, flip-flops, single and multi-port RAMs, complex bus resolution functions, and User Defined Primitives (UDPs).
It reads Verilog or VHDL gate-level netlists, WGL patterns, VCD files as well as Standard Delay Format (SDF) timing files.

F E AT U R E S O F T U R B O F A U L T

• Uses cycle-based simulation technology
• Advanced Cached-Concurrent (TM) Algorithm
• Low memory consumption
• User Definable Fault Detection Criteria
• Fault Tracing Capability
• Crash Recovery Capability
• Offers Multi-Pass, Incremental Simulation and Distributed Processing
• Accepts various inputs including reports from SynTest’s TurboScan(TM)-ATPG tool as well as from other EDA vendors’ ATPG tools.
• Offers a variety of reports/outputs, such as histograms, aggregated fault coverage reports, module level fault coverage reports, recommended list of patterns and a list of cut-off points.
• Supports toggle tests
• Flexible fault insertion points

Sereda Technologies Ltd

PO Box 444
Wokingham Berks UK
RG40 1ZR
Tel: +44 118 9782016
Fax: +44 118 9890424
Email:contact@ sereda-tech.co.uk