TurboDFT? contains a suite of very useful and powerful DFT integration tools. TurboDFT? allows users to automatically integrate and stitch DFT cores, whether they are created using DFT tools from SynTest or other vendors.

Rtlmsdb scripts and commands are provided for allowing users to automatically stitch DFT cores with or without boundary-scan control.

Thus, TurboDFT? brings *Ease of integration* benefit and eliminates the tedious, error-prone manual stitching process.

Besides the above function, TurboDFT? can assist users in creating top-level test benches for testing Memory and Logic BIST cores. Users can use the generated test benches to verify each BIST core that may be embedded deep in a hierarchical design.

TurboDFT? works with SynTest scan (TurboScan?), boundaryscan (TurboBSD?), memory BIST (TurboBIST-Memory?), and logic BIST (TurboBIST-Logic?) products to implement SoC level testability schemes enabling comprehensive board/system level tests.

BENEFITS

• Automatically integrate and stitch any combination of DFT cores, such as Scan cores, Memory BIST cores, Logic BIST cores, Analog BIST cores, IP cores, and the Boundary-scan (JTAG) core
• Automatically generate top-level test benches for Memory and Logic BIST cores with or without boundary-scan control
• Assist users in stitching DFT cores into their very deep hierarchical designs
• Eliminate the tedious, error-prone manual stitching process
• Input design can be RTL, Gate-level, or Mixed-level

Sereda Technologies Ltd

PO Box 444
Wokingham Berks UK
RG40 1ZR
Tel: +44 118 9782016
Fax: +44 118 9890424
Email:contact@ sereda-tech.co.uk