SynTest offers two versions of TurboCheck - TurboCheck- RTL- and TurboCheck-Gate- - to support different levels of checking throughout the design cycle.
With TurboCheck-RTL, designers can very quickly identify testability problems at the earliest stages of the design cycle, even before the often time-consuming logic synthesis process.

With TurboCheck-Gate, they can perform a structural level check on the final synthesized design to further identify and zero in on any final testability violations that could not be detected at the RTL level.
TurboCheck tools compute and report controllability and observability values according to the structure of the design and identify most common - and not so common - testability issues that could prevent efficient ATPG and fault simulation.

TurboCheck-Gate also offers automatic insertion of test points using any external scan selection algorithm and analyses the effect of the selection on the testability of the circuit.

B E N E F I T S

• Immediate feedback about potential design and testability problems
• Early detection of testability and synthesis constraint rule violations
• Versions for RTL and gate level tasks
• Provides testability analysis without test vectors
• Guides designers to the best testability solutions
• Selects scan and test points for improved fault coverage

Sereda Technologies Ltd

PO Box 444
Wokingham Berks UK
RG40 1ZR
Tel: +44 118 9782016
Fax: +44 118 9890424
Email:contact@ sereda-tech.co.uk