TurboBSD is a high performance boundary scan design suite that makes boundary scan design a fast and straightforward process.
It synthesizes boundary scan cells, the TAP controller and instruction registers.

The tool can output synthesizable Verilog and VHDL RTL codes that can be customized for your application and later synthesized using your own technology libraries. In addition to the standard IEEE 1149.1 public instructions, TurboBSD also supports custom ID code and private instructions.
After synthesis, it extracts the boundary scan chain information from the circuit and automatically creates the correct BSDL file. TurboBSD automatically generates implementation and fault model independent functional test sets to verify the integrity of the boundary scan logic.

TurboBSD also generates parametric tests (e.g., VOH, VOL, VIH, and VIL), and generates test patterns to control BIST operations using test information in the SVF format.

B E N E F I T S

• Automatically performs IEEE 1149.1 compliant boundary scan logic synthesis
• Automatically generates boundary scan description language (BSDL) files
• Automatically generates boundary scan test patterns, including verification and parametric test benches
• Supports RTL or gate level netlist generation in Verilog and VHDL formats
• Form-based boundary scan description entry for fast, error free operation
• Reduces boundary scan design time to minutes per design

Sereda Technologies Ltd

PO Box 444
Wokingham Berks UK
RG40 1ZR
Tel: +44 118 9782016
Fax: +44 118 9890424
Email:contact@ sereda-tech.co.uk