The TurboBIST-Logic (TM) is a powerful, yet easy-to-use, package to create Logic BIST circuits for embedded cores or IPs.
It is suitable for IP-based SOC designs to reduce the cost of manufacture tests and improve the quality by using "at-speed" testing. It generates BIST architecture for single clock, multiple clock and multiple frequency domains.

In these cases the "at-speed" strategy is used in TurboBIST-Logic?. The "atspeed" operation features a proprietary (patent-pending) multi-capture scheme which allows the core to be tested using "true" clocks; and a fault simulator, which supports stuck-at, transition, and path-delay (upcoming) fault models.

Other patent-pending features help implementation of the Logic BIST without adding to the timing closure burden in the back-end layout phase.

Sereda Technologies Ltd

PO Box 444
Wokingham Berks UK
RG40 1ZR

Tel / Fax:
+44 118 9782016

Email:contact@ sereda-tech.co.uk