The TurboBIST-Memory family of products from SynTest Technologies, Inc., includes tools for adding highly efficient BIST structures to all types of embedded memories including SRAMs, ROMs, SDRAMs and CAMs.

These tools, part of SynTest’s complete suite of testability analysis, scan synthesis, ATPG and fault simulation solutions, automatically synthesize the BIST logic surrounding the memory blocks and generate the test patterns needed to provide very high fault coverage testing of complete complex system-onchip ICs.

A single IEEE 1149.1 compliant TAP controller on the chip can be used to control multiple *BISTed* embedded memory cells of all types, as well as for controlling scan and boundary scan functions, thus keeping silicon overhead to the absolute minimum.

B E N E F I T S

• Automatically generates classical or user configurable test pattern sets
• Includes March C-, Moving Inversion March,March C++ and Checkerboard
• Allows simultaneous, multiple BIST memory test via a shared controller
• Supports embedded SRAMs, ROMs, SDRAMs and CAMs
• Outputs Verilog/VHDL synthesizable RTL code
• Outputs logic synthesis scripts
• Generates Verilog/VHDL test bench code automatically to reduce test design time

Sereda Technologies Ltd

PO Box 444
Wokingham Berks UK
RG40 1ZR
Tel: +44 118 9782016
Fax: +44 118 9890424
Email:contact@ sereda-tech.co.uk