DFT-PRO Plus

DFT-PRO Plus (TM) offers an integrated DFT solution covering scan synthesis and ATPG, memory Built-In Self-Test (BIST) synthesis and boundaryscan (BSD) synthesis.
The corresponding tools generate RTL blocks that fit seamlessly into an existing synthesis flow.

This gives the user the freedom to choose any commercially available logic and scan synthesis tools from vendors like Cadence, Incentia, Magma, Mentor, Synopsys or Synplicity and enables a one-pass RTL to GDSII synthesis flow. It also eases overall design floor planning.

Tools for checking DFT violations and integrating various DFT blocks and design RTL codes are also included in the package. The testability checker conducts an extensive DFT rules check at RTL. It offers automatic DFT repair at RTL by inserting repair logic. This alleviates the tedious manual coding at RTL to repair the DFT rule violations.

D F T - P R O P L U S
Integrated DFT solution for VirtualScan synthesis and ATPG, memory BIST synthesis and boundary-scan synthesis

B E N E F I T S :

  • Generates DFT blocks at RTL
    - Eases logic synthesis and design floor planning
  • Checks DFT violations at RTL
    - Averts time-consuming and costly post-synthesis changes
    - Auto-repair capability available
  • Generates XtremeCompact (TM) scan patterns using VirtualScan (TM) technology
    - Smaller test data volume and shorter test time
    - Reduces cost of semiconductor testing - 5x to 50x
    - Extends life of existing ATE for large SoC designs
  • High fault coverage
  • Smooth migration into existing scan ATPG flow

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Sereda Technologies Ltd

PO Box 444
Wokingham Berks UK
RG40 1ZR
Tel: +44 118 9782016
Fax: +44 118 9890424
Email:contact@ sereda-tech.co.uk